Warpage behavior on silicon semiconductor device: the impact of thick copper metallization

Electrochemical deposited (ECD) thick film copper on silicon substrate is one of the most challenging technological brick for semiconductor industry representing a relevant improvement from the state of art because of its excellent electrical and thermal conductivity compared with traditional materials, such as aluminum. The main technological factor that makes challenging the industrial implementation of thick copper layer is the severe wafer warpage induced by Cu annealing process, which negatively impacts the wafer manufacturability. The aim of presented work is the understanding of warpage variation during annealing process of ECD thick (20 µm) copper layer. Warpage is experimentally characterized at different temperature by means of Phase-Shift Moiré principle, according to different annealing profiles. Physical analysis is employed to correlated the macroscopic warpage behavior with microstructure modification. A linear Finite Element Model (FEM) is developed to predict the geometrically stress-curvature relation, comparing results with analytical models.